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multichannel ism band fsk/gfsk/ook/gook/ask transmitter adf7012 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2009 analog devices, inc. all rights reserved. features single-chip, low power uhf transmitter 75 mhz to 1 ghz frequency operation multichannel operation using fractional-n pll 2.3 v to 3.6 v operation on-board regulator programmable output power ?16 dbm to +14 dbm, 0.4 db steps data rates: dc to 179.2 kbps low current consumption 868 mhz, 10 dbm, 21 ma 433 mhz, 10 dbm, 17 ma 315 mhz, 0 dbm, 10 ma programmable low battery voltage indicator 24-lead tssop applications low cost wireless data transfer security systems rf remote controls wireless metering secure keyless entry general description the adf7012 is a low power fsk/gfsk/ook/gook/ask uhf transmitter designed for short-range devices (srds). the output power, output channels, deviation frequency, and mod- ulation type are programmable by using four, 32-bit registers. the fractional-n pll and vco with external inductor enable the user to select any frequency in the 75 mhz to 1 ghz band. the fast lock times of the fractional-n pll make the adf7012 suitable in fast frequency hopping systems. the fine frequency deviations available and pll phase noise performance facilitates narrow-band operation. there are five selectable modulation schemes: binary frequency shift keying (fsk), gaussian frequency shift keying (gfsk), binary on-off keying (ook), gaussian on-off keying (gook), and amplitude shift keying (ask). in the compensation register, the output can be moved in <1 ppm steps so that indirect com- pensation for frequency error in the crystal reference can be made. a simple 3-wire interface controls the registers. in power-down, the part has a typical quiescent current of <0.1 a. functional block diagram serial interface frequency compensation center frequency osc1 osc2 l1 l2 c vco clk out printed inductor agnd ce le data clk txdata txclk muxout rf gnd r set rf out c reg v dd dgnd dv dd fsk\gfsk ook\ask ook\ask clk r pfd/ charge pump - +fractional n vco pll lock detect muxout ldo regulator battery monitor pa 04617-0-001 figure 1.
adf7012 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ..................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? transistor count ........................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? 315 mhz ........................................................................................ 8 ? 433 mhz ........................................................................................ 9 ? 868 mhz ...................................................................................... 10 ? circuit description ......................................................................... 12 ? pll operation ............................................................................ 12 ? crystal oscillator ........................................................................ 12 ? crystal compensation register ................................................ 12 ? clock out circuit ....................................................................... 12 ? loop filter ................................................................................... 13 ? voltage-controlled oscillator (vco) ..................................... 13 ? voltage regulators ...................................................................... 13 ? fsk modulation .......................................................................... 13 ? gfsk modulation ...................................................................... 14 ? power amplifier ......................................................................... 14 ? gook modulation .................................................................... 15 ? output divider ........................................................................... 16 ? muxout modes....................................................................... 16 ? theory of operation ...................................................................... 17 ? choosing the external inductor value .................................... 17 ? choosing the crystal/pfd value ............................................. 17 ? tips on designing the loop filter ........................................... 18 ? pa matching ................................................................................ 18 ? transmit protocol and coding considerations ..................... 18 ? application examples .................................................................... 19 ? 315 mhz operation ................................................................... 20 ? 433 mhz operation ................................................................... 21 ? 868 mhz operation ................................................................... 22 ? 915 mhz operation ................................................................... 23 ? register descriptions ..................................................................... 24 ? register 0: r register ................................................................. 24 ? register 1: n-counter latch ..................................................... 25 ? register 2: modulation register ............................................... 26 ? register 3: function register .................................................... 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 6 /09rev. 0 to rev. a updated format .................................................................. universal changes to table 4 ............................................................................ 7 changes to crystal oscillator section ......................................... 12 changes to loop filter section ..................................................... 13 changes to gfsk modulation section ........................................ 14 changes to choosing the external inductor value section ..... 17 changes to component valuescrystal: 3.6864 mhz ............ 20 changes to component valuescrystal: 4.9152 mhz ............ 21 changes to component valuescrystal: 4.9152 mhz ............ 22 changes to component valuescrystal: 10 mhz .................... 23 added register headings throughout ........................................ 24 changes to ordering guide .......................................................... 28 10/04revision 0: initial version
adf7012 rev. a | page 3 of 28 specifications dv dd = 2.3 v C 3.6 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85c. table 1. parameter b version unit conditions/comments rf output characteristics operating frequency 75/1000 mhz min/max vco range adjustable using external inductor; divide-by-2, -4, -8 options may be required phase frequency detector f rf /128 hz min modulation parameters data rate fsk/gfsk 179.2 kbps using 1 mhz loop bandwidth data rate ask/ook 64 kbps based on us fcc 15.247 specifications for acp; higher data rates are achievable depending on local regulations deviation fsk/gfsk pfd/2 14 hz min for example, 10 mhz pfd ? deviation min = 610 hz 511 pfd/2 14 hz max for example, 10 mhz pfd ? deviation max = 311.7 khz gfsk bt 0.5 typ ask modulation depth 25 db max ook feedthrough (pa off ) ?40 dbm typ f rf = f vco ?80 dbm typ f rf = f vco /2 power amplifier parameters maximum power setting, dv dd = 3.6 v 14 dbm f rf = 915 mhz, pa is matched into 50 maximum power setting, dv dd = 3.0 v 13.5 dbm f rf = 915 mhz, pa is matched into 50 maximum power setting, dv dd = 2.3 v 12.5 dbm f rf = 915 mhz, pa is matched into 50 maximum power setting, dv dd = 3.6 v 14.5 dbm f rf = 433 mhz, pa is matched into 50 maximum power setting, dv dd = 3.0 v 14 dbm f rf = 433 mhz, pa is matched into 50 maximum power setting, dv dd = 2.3 v 13 dbm f rf = 433 mhz, pa is matched into 50 pa programmability 0.4 db typ pa output = ?20 dbm to +13 dbm power supplies dv dd 2.3/3.6 v min/v max current consumption 315 mhz, 0 dbm/5 dbm 8/14 ma typ dv dd = 3.0 v, pa is matched into 50 , i vco = min 433 mhz, 0 dbm/10 dbm 10/18 ma typ 868 mhz, 0 dbm/10 dbm/14 dbm 14/21/32 ma typ 915 mhz, 0 dbm/10 dbm/14 dbm 16/24/35 ma typ vco current consumption 1/8 ma min/max vco current consumption is programmable crystal oscillator current consumption 190 a typ regulator current consumption 280 a typ power-down current 0.1/1 a typ/max reference input crystal reference frequency 3.4/26 mhz min/max single-ended reference frequency 3.4/26 mhz min/max crystal power-on time 3.4 mhz/26 mhz 1.8/2.2 ms typ ce to clock enable valid single-ended input level cmos levels refer to the logic inputs parameter. applied osc 2, oscillator circuit disabled.
adf7012 rev. a | page 4 of 28 parameter b version unit conditions/comments phase-locked loop parameters vco gain 315 mhz 22 mhz/v typ vco divide-by-2 active 433 mhz 24 mhz/v typ vco divide-by-2 active 868 mhz 80 mhz/v typ 915 mhz 88 mhz/v typ vco tuning range 0.3/2.0 v min/max spurious (ivco min/max) ?65/?70 dbc i vco is programmable charge pump current setting [00] 0.3 ma typ referring to db[7:6] in function register setting [01] 0.9 ma typ referring to db[7:6] in function register setting [10] 1.5 ma typ referring to db[7:6] in function register setting [11] 2.1 ma typ referring to db[7:6] in function register phase noise (in band) 1 315 mhz ?85 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 2 ma 433 mhz ?83 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 2 ma 868 mhz ?80 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 3 ma 915 mhz ?80 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 3 ma phase noise (out of band) 1 315 mhz ?103 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 2 ma 433 mhz ?104 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 2 ma 868 mhz ?115 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 3 ma 915 mhz ?114 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 3 ma harmonic content (second) 2 ?20 dbc typ f rf = f vco harmonic content (third) 2 ?30 dbc typ harmonic content (others) 2 ?27 dbc typ harmonic content (second) 2 ?24 dbc typ f rf = f vco /n (where n = 2, 4, 8) harmonic content (third) 2 ?14 dbc typ harmonic content (others) 2 ?19 dbc typ logic inputs input high voltage, v inh 0.7 dv dd v min input low voltage, v inl 0.2 dv dd v max input current, i inh /i inl 1 a max input capacitance, c in 4.0 pf max logic outputs output high voltage, v oh dv dd ? 0.4 v min cmos output chosen output high current, i oh , 500 a max output low voltage, v ol 0.4 v max i ol = 500 a 1 measurements made with n frac = 2048. 2 measurements made without harmonic filter.
adf7012 rev. a | page 5 of 28 timing characteristics dv dd = 3 v 10%; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data-to-clock setup time t 3 10 ns min data-to-clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock-to-le setup time t 7 20 ns min le pulse width clk data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04617-0-002 figure 2. timing diagram
adf7012 rev. a | page 6 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating dv dd to gnd (gnd = agnd = dgnd = 0 v) ?0.3 v to +3.9 v digital i/o voltage to gnd ?0.3 v to dv dd + 0.3 v analog i/o voltage to gnd ?0.3 v to dv dd + 0.3 v operating temperature range ?40c to +85c maximum junction temperature 150c tssop ja thermal impedance 150.4c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of 1 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. transistor count 35819 (cmos) esd caution
adf7012 rev. a | page 7 of 28 pin configuration and fu nction descriptions adf7012 top view (not to scale) dv dd 1 c reg1 2 cp out 3 txdata 4 txclk 5 c reg2 r set agnd dv dd rf out 24 23 22 21 20 muxout 6 dgnd 7 osc1 8 osc2 9 rf gnd vco in c vco l2 19 18 17 16 clk out 10 clk 11 l1 ce 15 14 data 12 le tssop 13 04617-0-003 figure 3. pin configuration table 4. pin functional descriptions pin no. mnemonic description 1 dv dd positive supply for the digital circuitry. this must be between 2.3 v and 3.6 v. deco upling capacitors to the analog ground plane should be placed as cl ose as possible to this pin. 2 c reg1 a 1 f capacitor should be added at c reg to reduce regulator noise and improve stability. a reduced capacitor improves regulator power-on time, but may cause higher spurious noise. 3 cp out charge pump output. this output generates current pulses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 4 txdata digital data to be t ransmitted is input on this pin. 5 txclk gfsk and gook only. this clock output is used to synchron ize microcontroller data to the txdata pin of the adf7012. the clock is provided at the same frequency as the data rate. the microcontroller updates txdata on the falling edge of txclk. the rising edge of txclk is used to sample txdata at the midpoint of each bit. 6 muxout provides the lock_detect signal. this signal is used to determine if the pll is locked to the correct frequency. it al so provides other signals, such as regulator_ready, which is an indi cator of the status of the serial interface regulator, and a voltage monitor (see the muxout modes section for more information). 7 dgnd ground for digital section. 8 osc1 the reference crystal should be connected between this pin and osc2. 9 osc2 the reference crystal should be connected between this pi n and osc1. a tcxo reference may be used, by driving this pin with cmos levels, and powering down the crystal oscillator bit in software. 10 clk out a divided-down version of the crystal reference with output driver. the digital clock output may be used to drive several other cmos inputs, such as a microcontroller clock. the output has a 50:50 mark-space ratio. 11 clk serial clock input. this serial clock is used to clock in the serial data to the register s. the data is latched into the 32-bit shift register on the clk rising edge. this input is a high impedance cmos input. 12 data serial data input. the serial data is loaded msb firs t with the two lsbs being the control bits. this is a high impedan ce cmos input. 13 le load enable, cmos input. when le goes high, the data stor ed in the shift registers is loaded into one of the four latches , the latch being selected using the control bits. 14 ce chip enable. bringing ce low puts the adf7012 into comp lete power-down, drawing < 1a. register values are lost when ce is low and the part must be re programmed once ce is brought high. 15 l1 connected to external pr inted or discrete inductor. see choosing the external inductor value for advice on the value of the inductor to be connected between l1 and l2. 16 l2 connected to external printed or discrete inductor. 17 c vco a 22 nf capacitor should be tied between the c vco and c reg2 pins. this line should run underneath the adf7012. this capacitor is necessary to ensure stable vco operation. 18 vco in the tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (vco). the higher the tuning voltage, the higher the output frequency. 19 rf gnd ground for output stage of transmitter. 20 rf out the modulated signal is available at this pin. output power levels are from C16 dbm to +12 dbm. the output should be impedance matched using suitable comp onents to the desired load. see the pa matching section. 21 dv dd voltage supply for vco and pa section. this should have the same supply as dv dd (pin 1), and should be between 2.3 v and 3.6 v. place decoupling capacitors to the analog ground plane as close as possible to this pin. 22 agnd ground pin for th e rf analog circuitry. 23 r set external resistor to set charge pump current and some internal bias currents. use 3.6 k as default. 24 c reg2 add a 470 nf capacitor at c reg to reduce regulator noise and improve stability. a reduced capacitor improves regulator power-on time and phase noise, but may have stab ility issues over the supply and temperature.
adf7012 rev. a | page 8 of 28 typical performance characteristics 315 mhz phase noise (hz) dbc (hz) ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-004 = normal frequency = 9.08 khz level = ?84.47dbc/hz figure 4. phase noise responsedv dd = 3.0 v, i cp = 0.86 ma i vco = 2.0 ma, f out = 315 mhz, pfd = 3.6864 mhz, pa bias = 5.5 ma 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-005 1ma 2 1 center 315mhz 50khz/ span 500khz ref lvl 5dbm 0.45dbm 315.05060120mhz 30db dbm rf att unit 5khz 5khz 500ms rbw vbw swt a figure 5. fsk modulation, power = 0 dbm, data rate = 1 kbps, f deviation = 50 khz 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-006 1ma 1 center 315mhz 40mhz/ d1 ?41.5dbm d2 ?49dbm span 400mhz ref lvl 5dbm 0.31dbm 315.40080160mhz 30db dbm rf att unit 500khz 500khz 5ms rbw vbw swt a 1 [t1] 0.31dbm 315.40080160mhz figure 6. spurious comp onentsmeets fcc specs 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-007 1ma 1 center 3.5mhz 700mhz/ d1 ?41.5dbm span 7ghz ref lvl 5dbm 0.27dbm 308.61723447mhz 30db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a 3 2 4 2 [t1] 1 [t1] 0.27dbm 308.61723447mhz ?35.43dbm 631.26252505mhz 3 [t1] 4 [t1] ?11.48dbm 939.87975952mhz ?34.11dbm 1.26252505ghz figure 7. harmonic response, rf out matched to 50 , no filter 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-008 1ma sgl 1 center 3.5mhz 700mhz/ d1 ?41.5dbm span 7ghz ref lvl 5dbm 0.18dbm 308.61723447mhz 30db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a 3 2 4 2 [t1] 1 [t1] 0.18dbm 308.61723447mhz ?50.53dbm 631.26252505mhz 3 [t1] 4 [t1] ?42.93dbm 939.87975952mhz ?55.48dbm 1.26252505ghz figure 8. harmonic response, fifth-order butterworth filter 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-009 1ma 1 2 3 center 315mhz 50khz/ span 500khz ref lvl 5dbm 20.33dbm 26.55310621khz 30db dbm rf att unit 5khz 5khz 500ms rbw vbw swt a 3 [t1] 2 [t1] 1 [t1] ?3.49dbm 315.00012525mhz ?20.33db 26.55310621khz ?20.85db ?27.55511022khz figure 9. ook modulation, power = 0 dbm, data rate = 10 kbps
adf7012 rev. a | page 9 of 28 433 mhz 04617-0-010 1 2.00v/ 2 1 2 1.00v/ 1.50ms 720mv 500 s trig'd 1 clkout ce figure 10. crystal power-on time, 4 mhz, time = 1.6 ms phase noise (hz) dbc (hz) ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-011 = normal frequency = 393.38 khz level = ?102.34dbc/hz figure 11. phase noise responsei cp = 2.0 ma, i vco = 2.0 ma, rf out = 433.92 mhz, pfd = 4 mhz, pa bias = 5.5 ma 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-012 1ma 1 start 433.05mhz 174khz/ stop 434.79khz ref lvl 15dbm 5.60dbm 433.91158317mhz 40db dbm rf att unit 10khz 300khz 44ms rbw vbw swt a d1 ?36dbm figure 12. fsk modulation, power = 10 dbm, data rate = 38.4 kbps, f deviation = 19.28 khz 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-013 1ma 1 center 433.9500601mhz 3.2mhz/ span 32mhz ref lvl 15dbm 10.01dbm 433.91158317mhz 40db dbm rf att unit 30khz 30khz 90ms rbw vbw swt a d1 ?36dbm figure 13. spurious componentsmeets etsi specs 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-014 1ma 1 center 3.5ghz 700mhz/ span 7ghz ref lvl 15dbm 10.10dbm 434.86973948mhz 40db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a d1 ?36dbm d1 ?30dbm 2 3 4 2 [t1] 1 [t1] 10.10dbm 434.86973948mhz ?15.25dbm 869.73947896mhz 3 [t1] 4 [t1] ?5.12dbm 1.30460922ghz ?17.57dbm 1.73947896ghz figure 14. harmonic response, rf out matched to 50 , no filter 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-015 1ma sgl 1 center 3.5ghz 700mhz/ span 7ghz ref lvl 15dbm 9.51dbm 434.86973948mhz 40db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a d1 ?36dbm d1 ?30dbm 2 3 4 2 [t1] 1 [t1] 9.51dbm 434.86973948mhz ?33.75dbm 869.73947896mhz 3 [t1] 4 [t1] ?43.60dbm 1.30460922ghz ?43.44dbm 1.73947896ghz figure 15. harmonic response, fifth-order butterworth filter
adf7012 rev. a | page 10 of 28 868 mhz phase noise (hz) dbc (hz) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-016 = normal frequency = 251.3 khz level = ?99.39dbc/hz figure 16. phase noise responsei cp = 2.5 ma, i vco = 1.44 ma, rf out = 868.95 mhz, pfd = 4.9152 mhz, power = 12.5 dbm, pa bias = max 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-017 1ma ln center 868.944489mhz 60khz/ span 600khz ref lvl 15dbm ?40.44dbm 869.20000000mhz 30db ?20dbm dbm rf att mixer unit 10khz 10khz 15ms rbw vbw swt a d2 ?36dbm 1 2 2 [t1] 1 [t1] 40.44dbm 869.20000000mhz 8.02dbm 868.96673347mhz 1max figure 17. fsk modulation, power = 12.5 dbm, data rate = 38.4 kbps, f deviation = 19.2 khz 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-018 1ma ln start 856.5mhz 2.5mhz/ stop 881.5mhz ref lvl 15dbm 12.55dbm 869.025050100mhz 30db ?20dbm dbm rf att mixer unit 2khz 2khz 16s rbw vbw swt a d2 ?36dbm d1 ?54dbm 1 2 3 1max 2 [t1] 3 [t1] 1 [t1] 12.55dbm 869.02505010mhz ?57.89dbm 859.16695500mhz ?81.97dbm 862.00000000mhz figure 18. spurious componentsmeets etsi specs 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-019 1ma 1 center 3.8ghz 640mhz/ span 6.4ghz ref lvl 15dbm 12.27dbm 869.33867735mhz 40db dbm rf att unit 1mhz 1mhz 16ms rbw vbw swt a d1 ?30dbm 2 3 4 2 [t1] 1 [t1] 12.27dbm 869.33867735mhz ?4.00dbm 1.72865731ghz 3 [t1] 4 [t1] ?16.88dbm 2.59699399ghz ?15.06dbm 3.46913828ghz 1max figure 19. harmonic response, rf out matched to 50 , no filter 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-020 1ma ln start 3.8ghz 640mhz/ span 6.4ghz ref lvl 15dbm 10.39dbm 869.33867735mhz 30db ?20dbm dbm rf att mixer unit 1khz 1khz 10ms rbw vbw swt a d2 ?30dbm 1 2 3 1max 3 [t1] 2 [t1] 1 [t1] 10.39dbm 869.33867735mhz ?50.92dbm 1.72000000ghz ?50.40dbm 2.59600000ghz figure 20. harmonic response, fifth-order chebyshev filter
adf7012 rev. a | page 11 of 28 915 mhz phase noise (hz) dbc (hz) ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-021 = normal frequency = 992.38 khz level = ?102.34dbc/hz figure 21. phase noise responsei cp = 1.44 ma, i vco = 3.0 ma, rf out = 915.2 mhz, pfd =10 mhz, power = 10 dbm, pa bias = 5.5 ma 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-036 1ma center 915.190982mhz 50khz/ span 500khz ref lvl 15dbm 3.88dbm 915.19098196mhz 40db dbm rf att unit 10khz 300khz 15ms rbw vbw swt a 1 1max figure 22. fsk modulation, power = 10 dbm, data rate = 38.4 kbps, f deviation = 19.2 khz 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-037 1ma sgl center 915.2mhz 40mhz/ span 400mhz ref lvl 15dbm 9.94dbm 915.23167977mhz 40db dbm rf att unit 10khz 300khz 100ms rbw vbw swt a * 1 d1 ?49.5dbm d1 ?41.5dbm figure 23. spurious componentsmeets fcc specs 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-038 1ma 1 center 3.8ghz 640mhz/ span 6.4gh z ref lvl 15dbm 10.25dbm 907.81563126mhz 40db dbm rf att unit 50mhz 50mhz 6.4s rbw vbw swt a d1 ?41.5dbm 2 3 4 2 [t1] 1 [t1] 10.25dbm 907.81563126mhz ?10.06dbm 1.83126253ghz 3 [t1] 4 [t1] ?20.29dbm 2.74188377ghz ?17.50dbm 3.65250501ghz 1max figure 24. harmonic response, rf out matched to 50 , no filter 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-039 1ma 1 center 3.8ghz 640mhz/ span 6.4ghz ref lvl 15dbm 9.06dbm 907.81563126mhz 40db dbm rf att unit 50mhz 50mhz 6.4s rbw vbw swt a d1 ?41.5dbm 2 3 4 2 [t1] 1 [t1] 9.06dbm 907.81563126mhz ?48.40dbm 1.83126253ghz 3 [t1] 4 [t1] ?46.22dbm 2.74188377ghz ?46.96dbm 3.65250501ghz 1max figure 25. harmonic response, fifth-order chebyshev filter
adf7012 rev. a | page 12 of 28 circuit description pll operation a fractional-n pll allows multiple output frequencies to be generated from a single-reference oscillator (usually a crystal) simply by changing the programmable n value found in the n register. at the phase frequency detector (pfd), the reference is compared to a divided-down version of the output frequency (vco/n). if vco/n is too low a frequency, typically the output frequency is lower than desired, and the pfd and charge-pump combination sends additional current pulses to the loop filter. this increases the voltage applied to the input of the vco. because the vco of the adf7012 has a positive frequency vs. voltage characteristic, any increase in the v tune voltage applied to the vco input increases the output frequency at a rate of kilovolts, the tuning sensitivity of the vco (mhz/v). at each interval of 1/pfd seconds, a comparison is made at the pfd until the pfd and charge pump eventually force a state of equilibrium in the pll where pfd frequency = vco/n. at this point, the pll can be described as locked. n r cp pfd crystal/r loop filter fvco vco vco/n 04617-0-022 figure 26. fractional-n pll nf r nf f pfd crystal out = = (1) for a fractional-n pll ? ? ? ? ? ? += 12 2 frac int pfd out n nff (2) where n frac can be bits m1 to m12 in the fractional-n register. crystal oscillator the on-board crystal oscillator circuitry ( figure 27 ) allows an inexpensive quartz crystal to be used as the pll reference. the oscillator circuit is enabled by setting xoeb low. it is enabled by default on power-up and is disabled by bringing ce low. errors in the crystal can be corrected using the error correction register within the r register. a single-ended reference may be used instead of a crystal, by applying a square wave to the osc2 pin, with xoeb set high. osc1 cp1 cp2 osc2 04617-0-023 figure 27. oscillator circuit on the adf7012 two parallel resonant capacitors are required for oscillation at the correct frequencythe value of these depend on the crystal specification. they should be chosen so that the series value of capacitance added to the pcb track capacitance adds to give the load capacitance of the crystal, usually 20 pf. track capacitance values vary between 2 pf to 5 pf, depending on board layout. where possible, to ensure stable frequency operation over all conditions, capacitors should be chosen so that they have a very low temperature coefficient and/or opposite temperature coefficients typically, for a 10 mhz crystal with 20 pf load capacitance, the oscillator circuit can tolerate a crystal esr value of 50 . the esr tolerance of the adf7012 decreases as crystal fre- quency increases, but this can be offset by using a crystal with lower load capacitance. crystal compensation register the adf7012 features a 15-bit fixed modulus, which allows the output frequency to be adjusted in steps of fpfd/15. this fine resolution can be used to easily compensate for initial error and temperature drift in the reference crystal. f adjust = f step fec (3) where: f step = fpfd/215 fec = bit f1 to bit f11 in the r register note that the notation is twos complement, so f11 represents the sign of the fec number. example f pfd = 10 mhz f adjust = ?11 khz f step = 10 mhz/2 15 = 305.176 hz fec = ?11 khz/305.17 hz = ?36 = ?(00000100100) = 11111011100 = 0x7dc clock out circuit the clock out circuit takes the reference clock signal from the crystal oscillator section and supplies a divided-down 50:50 mark-space signal to the clk out pin. an even divide from 2 to 30 is available. this divide is set by the db[19:22] in the r register. on power-up, the clk out defaults to divide by 16.
adf7012 rev. a | page 13 of 28 04617-0-024 dv dd clk out enable bit clk out osc1 divider 1 to 15 2 figure 28. clkout stage the output buffer to clk out is enabled by setting bit db4 in the function register high. on power-up, this bit is set high. the output buffer can drive up to a 20 pf load with a 10% rise time at 4.8 mhz. faster edges can result in some spurious feedthrough to the output. a small series resistor (50 ) can be used to slow the clock edges to reduce these spurs at f clk . loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. a typical loop filter design is shown in figure 29. 04617-0-025 charge pump out vco figure 29. typical loop filter in fsk, it is recommended that the loop bandwidth be a minimum of two to three times the data rate. widening the lbw excessively reduces the time spent jumping between frequencies, but results in reduced spurious attenuation. see the tips on designing the loop filter section. for ook/ask systems, a wider loop bandwidth than for fsk systems is desirable. the sudden large transition between two power levels results in vco pulling (vco temporarily goes to incorrect frequency) and can cause a wider output spectrum. by widening the loop bandwidth a minimum of 10 the data rate, vco pulling is minimized because the loop settles quickly back to the correct frequency. a free design tool, the adi srd design studio ?, can be used to design loop filters for the analog devices family of transmitters. voltage-controlled oscillator (vco) the adf7012 features an on-chip vco with an external tank inductor, which is used to set the frequency range. the center frequency of oscillation is governed by the internal varactor capacitance and that of the external inductor combined with the bond-wire inductance. an approximation for this is given in equation 4. for a more accurate selection of the inductor, see the section choosing the external inductor value . ( the varactor capacitance can be adjusted in software to increase the effective vco range by writing to the va1 and va2 bits in the r register. under typical conditions, setting va1 and va2 high increases the center frequency by reducing the varactor capacitance by approximately 1.3 pf. figure 37 shows the variation of vco gain with frequency. vco gain is important in determining the loop filter design predictable changes in vco gain resulting in a change in the loop filter bandwidth can be offset by changing the charge- pump current in software. vco bias current vco bias current may be adjusted using bits vb1 to vb4 in the function register. additional bias current will reduce spurious levels, but increase overall current consumption in the part. a bias value of 0x5 should ensure oscillation at most frequencies and supplies. settings 0x0, 0xe , and 0xf are not recommended. setting 0x3 and setting 0x4 are recommended under most conditions. improved phase noise can be achieved for lower bias currents. voltage regulators there are two band gap voltage regulators on the adf7012 providing a stable 2.25 v internal supply: a 2.2 f capacitor (x5r, np0) to ground at c reg1 and a 470 nf capacitor at c reg2 should be used to ensure stability. the internal reference ensures consistent performance over all supplies and reduces the current consumption of each of the blocks. the combination of regulators, band gap reference, and biasing typically consume 1.045 ma at 3.0 v and can be powered down by bringing the ce line low. the serial interface is supplied by regulator 1, so powering down the ce line causes the contents of the registers to be lost. the ce line must be high and the reg- ulators must be fully powered on to write to the serial interface. regulator power-on time is typically 100 s and should be taken into account when writing to the adf7012 after power-up. alternatively, regulator status may be monitored at the muxout pin once ce has been asserted, because muxout defaults to the regulator ready signal. once regulator_ready is high, the regulator is powered up and the serial interface is active. fsk modulation fsk modulation is performed internally in the pll loop by switching the value of the n register based on the status of the txdata line. the txdata line is sampled at each cycle of the pfd block (every 1/f pfd seconds). when txdata makes a low-to-high transition, an n value representing the deviation frequency is added to the n value representing the center frequency. immediately the loop begins to lock to the new frequency of f center + f deviation . conversely, when txdata makes a high-to-low transition, the n value representing the deviation is subtracted from the pll n value representing the center frequency and the loop transitions to f center ? f deviation . ) fixed var ext int vco ccll f ++ = )( 2 1 (4)
adf7012 rev. a | page 14 of 28 04617-0-026 vco n third-order - modulator pfd/ charge pump 4r integer-n fractional-n pa stage ?f dev +f dev txdata fsk deviation frequency figure 30. fsk implementation the deviation from the center frequency is set using the d1 to d9 bits in the modulation register. the frequency deviation may be set in steps of 14 2 )( pfd step f hzf = (5) the deviation frequency is therefore 14 2 )( number modulation f hz f pfd deviation = (6) where modulationnumber is set by bit d1 to bit d9. the maximum data rate is a function of the pll lock time (and the requirement on fsk spectrum). because the pll lock time is reduced by increasing the loop-filter bandwidth, highest data rates can be achieved for the wider loop filter bandwidths. the absolute maximum limit on loop filter bandwidth to ensure stability for a fractional-n pll is f pfd /7. for a 20 mhz pfd frequency, the loop bandwidth could be as high as 2.85 mhz. fsk modulation is selected by setting the s1 and s2 bits in the modulation register low. gfsk modulation gaussian frequency shift keying (gfsk) represents a filtered form of frequency shift keying. the data to be modulated to rf is prefiltered digitally using a finite impulse response filter (fir). the filtered data is then used to modulate the sigma- delta fractional-n to generate spectrally-efficient fsk. fsk consists of a series of sharp transitions in frequency as the data is switched from one level to another. the sharp switching generates higher frequency components at the output, resulting in a wider output spectrum. with gfsk, the sharp transitions are replaced with up to 128 smaller steps. the result is a gradual change in frequency. as a result, the higher frequency components are reduced and the spectrum occupied is reduced significantly. gfsk does require some additional design work as the data is only sampled once per bit, and so the choice of crystal is important to ensure the correct sampling clock is generated. for gfsk and gook, the incoming bit stream to be trans- mitted needs to be synchronized with an on-chip sampling clock which provides one sample per bit to the gaussian fir filter. to facilitate this, the sampling clock is routed to the txclk pin where data is fetched from the host microcontroller or microprocessor on the falling edge of txclk, and the data is sampled at the midpoint of each bit on txclks rising edge. inserting external rc lpfs on txdata and txclk lines creates smoother edge transitions and improves spurious performance. as an example, suitable components are a 1 k resistor and a 10 nf capacitor for a data rate of 5 kbps. fetch sample fetch sample fetch sample fetch adf7012 c i/o int txdata txclk 04617-0-040 figure 31. txclk/txdata synchronization. the number of steps between symbol 0 and symbol 1 is determined by the setting for the index counter. the gfsk deviation is set up as 12 m 2 2 )hz( = pfd deviation f gfsk (7) where m is the mod control (bit mc1 to bit mc3 in the modulation register). the gfsk sampling clock samples data at the data rate er indexcount tor dividerfac f bps datarate pfd = )( (8) where the dividerfactor is set by bit d1 to bit d7, and the indexcounter is set by bit ic1 and bit ic2 in the modulation register. power amplifier the output stage is based on a class e amplifier design, with an open-drain output switched by the vco signal. the output control consists of six current mirrors operating as a program- mable current source. to achieve maximum voltage swing, the rf out pin needs to be biased at dv dd . a single pull-up inductor to dv dd ensures a current supply to the output stage; pa is biased to dv dd volts, and with the correct choice of value transforms the impedance. the output power can be adjusted by changing the value of bit p1 to bit p6. typically, this is p1 to p6 output ?20dbm at 0x0, and 13 dbm at 0x7e at 868 mhz, with the optimum matching network.
adf7012 rev. a | page 15 of 28 the nonlinear characteristic of the output stage results in an output spectrum containing harmonics of the fundamental, especially the third and fifth. to meet local regulations, a low- pass filter usually is required to filter these harmonics. the output stage can be powered down by setting bit pd2 in the function register low. gook modulation gaussian on-off keying (gook) represents a prefiltered form of ook modulation. the usually sharp symbol transitions are replaced with smooth gaussian-filtered transitions with the result being a reduction in frequency pulling of the vco. frequency pulling of the vco in ook mode can lead to a wider than desired bandwidth, especially if it is not possible to increase the loop filter bandwidth to > 300 khz. the gook sampling clock samples data at the data rate: er indexcount tor dividerfac f bps datarate pfd = )( (9) bit d1 to bit d6 represent the output power for the system for a positive data bit. divider factor = 0x3f represents the maximum possible deviation from pa at minimum to pa at maximum output. note that pa output level bits in register 2 are defunct. an index counter setting of 128 is recommended. figure 32 shows the step response of the gaussian fir filter. an index counter of 16 is demonstrated for simplicity. while the pre-filter data would switch the pa directly from off to on with a low-to-high data transition, the filtered data gradually increases the pa output in discrete steps. this has the effect of making the output spectrum more compact. 04617-0-041 pa setting pre-filter data (0 to 1 transition) discretized filter output 16 (max) 15 14 13 12 11 10 9 8 7 5 4 3 2 1 (pa off) 6 figure 32. varying pa output for gook (index counter = 16). as is the case with gfsk, gook requires the bit stream applied at txdata to be synchronized with the sampling clock, txclk (see the gfsk modulation section). frequency (mhz) power (dbm) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 909.43 910.43 ook gook 910.93 04617-0-043 figure 33. gook vs. ook frequency spectra (narrow-band measurement) frequency (mhz) power (dbm) 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?90 ?80 885.43 910.43 935.93 04617-0-044 gook ook figure 34. gook vs. ook frequency spectra (wideband measurement)
adf7012 rev. a | page 16 of 28 battery voltage readback output divider by setting muxout to 1010 to 1101, the battery voltage can be estimated. the battery measuring circuit features a voltage divider and a comparator where the divided-down supply voltage is compared to the regulator voltage. an output divider is a programmable divider following the vco in the pll loop. it is useful when using the adf7012 to generate frequencies of < 500 mhz. 04617-0-042 pfd cp pa output divider loop filter reference divider n 1/2/4/8 vco table 6. muxout muxout high muxout low 1010 dv dd < 2.35 v dv dd > 2.35 v 1011 dv dd < 2.75 v dv dd > 2.75 v 1100 dv dd < 3.0 v dv dd > 3.0 v 1101 dv dd < 3.25 v dv dd > 3.25 v figure 35. output divi der location in pll the output divider may be used to reduce feedthrough of the vco by amplifying only the vco/2 component, restricting the vco feedthrough to leakage. the accuracy of the measurement is limited by the accuracy of the regulator voltage and the internal resistor tolerances. because the divider is in loop, the n register values should be set up according to the usual formula. however, the vco gain (k v ) should be scaled according to the divider setting, as shown in the following example: regulator ready the regulator has a power-up time, dependant on process and the external capacitor. the regulator ready signal indicates that the regulator is fully powered, and that the serial interface is active. this is the default setting on power-up at muxout. f out = 433 mhz f vco = 866 mhz k v @ 868 mhz = 60 mhz/v digital lock detect therefore, k v for loop filter design = 30 mhz/v. the divider value is set in the r register. table 5. od1 od2 divider status 0 0 divider off 0 1 divide by 2 1 0 divide by 4 1 1 divide by 8 digital lock detect indicates that the status of the pll loop. the pll loop takes time to settle on power-up and when the frequency of the loop is changed by changing the n value. when lock detect is high, the pfd has counted a number of consecutive cycles where the phase error is < 15 ns. the lock detect precision bit in the function register determines whether this is three cycles (ldp = 0), or five cycles (ldp = 1). it is recommended that ldp be set to 1. the lock detect is not completely accurate and goes high before the output has settled to exactly the correct frequency. in general, add 50% to the indicated lock time to obtain lock time to within 1 khz. the lock detect signal can be used to decide when the power amplifier (pa) should be enabled. muxout modes the muxout pin allows the user access to various internal signals in the transmitter, and provides information on the pll lock status, the regulator, and the battery voltage. the muxout is accessed by programming bits m1 to m4 in the function register and observing the signal at the muxout pin. r divider muxout provides the output of the r divider. this is a narrow pulsed digital signal at frequency f pfd . this signal may be used to check the operation of the crystal circuit and the r divider. r divider/2 is a buffered version of this signal at f pfd /2.
adf7012 rev. a | page 17 of 28 theory of operation choosing the external inductor value the adf7012 allows operation at many different frequencies by choosing the external vco inductor to give the correct output frequency. figure 36 shows both the minimum and maximum frequency vs. the inductor value. these are measurements based on 0603 cs type inductors from coilcraft, and are intended as guidelines in choosing the inductor because board layout and inductor type varies between applications. the inductor value should be chosen so that the vco is cen- tered at the correct frequency. when locked, the vco tuning voltage can be between 0.2 v and 2.1 v. this voltage can be measured at pin 18 (vco in ). to ensure operation over temperature and from part to part, an inductor should be chosen so that the tuning voltage is ~1 v at the desired output frequency. min (meas) max (meas) min (eqn) max (eqn) inductance (nh) frequency (mhz) 1200 1000 900 1100 700 800 500 400 600 300 01 0 51 52 03 0 25 35 04617-0-031 figure 36. output frequency vs. external inductor value i bias = 2.0 ma. for frequencies between 270 mhz and 550 mhz, it is recom- mended to operate the vco at twice the desired output frequency and use the divide-by-2 option. this ensures reliable operation over temperature and supply. for frequencies between 130 mhz and 270 mhz, it is recom- mended to operate the vco at four times the desired output frequency and use the divide-by-4 option. for frequencies below 130 mhz, it is best to use the divide- by-8 option. it is not necessary to use the vco divider for frequencies above 550 mhz. adisimsrd design studio is a design tool which can perform the frequency calculations for the adf7012, and is available at www. analog.com . choosing the crystal/pfd value the choice of crystal value is an important one. the pfd frequency must be the same as the crystal value or an integer division of it. the pfd determines the phase noise, spurious levels and location, deviation frequency, and the data rate in the case of gfsk. the following sections describe some factors to consider when choosing the crystal value. standard crystal values standard crystal values are 3.6864 mhz, 4 mhz, 4.096 mhz, 4.9152 mhz, 7.3728 mhz, 9.8304 mhz, 10 mhz, 11.0592 mhz, 12 mhz, and 14.4792 mhz. crystals with these values are usually available in stock and cost less than crystals with nonstandard values. reference spurious levels reference spurious levels (spurs) occur at multiples of the pfd frequency. the reference spur closest to the carrier is usually highest with the spur further out being attenuated by the loop filter. the level of reference spur is lower for lower pfd frequencies. in designs with high output power where spurious levels are the main concern, a lower pfd frequency (<5 mhz) may be desirable. beat note spurs beat note spurs are spurs occurring for very small or very large values in the fractional register. these are quickly attenuated by the loop filter. selection of the pfd therefore determines their location, and ensures that they have negligible effect on the transmitter spectrum. phase noise the phase noise of a frequency synthesizer improves by 3 db for every doubling of the pfd frequency. because acp is related to the phase noise, the pfd may be increased to reduce the acp in the system. pfd frequencies of < 5 mhz typically deliver sufficient phase noise performance for most systems. deviation frequency the deviation frequency is adjustable in steps of 14 2 )( pfd step f hzf = (10) to get the exact deviation frequency required, ensure f step is a factor of the desired deviation.
adf7012 rev. a | page 18 of 28 tips on designing the loop filter the loop filter design is crucial in ensuring stable operation of the transmitter, meeting adjacent channel power (acp) specifications, and meeting spurious requirements for the relevant regulations. adisimsrd design studio? is a free tool available to aid the design of loop filters. the user enters the desired frequency range, the reference crystal and pfd values, and the desired loop bandwidth. adisimsrd design studio gives a good starting point for the filter, and the filter can be further optimized based on the criteria below. setting tuning sensitivity value the tuning sensitivity or kv, usually denoted in mhz/v, is required for the loop filter design. it refers to the amount that a change of a volt in the voltage applied to the vco in pin, changes the output frequency. typical data for the adf7012 over a frequency range is shown. frequency (mhz) k v (mhz/v) 120 100 60 80 40 20 0 200 400300 600500 800 900 1000 700 1100 004617-0-032 figure 37. kv vs. vco frequency charge-pump current the charge-pump current allows the loop filter bandwidth to be changed using the registers. the loop bandwidth reduces as the charge pump current is reduced and vice versa. selecting loop filter bandwidth data rate the loop filter bandwidth should usually be at two to three times the data rate. this ensures that the pll has ample time to jump between the mark and space frequencies. acp in the case where the acp specifications are difficult to meet, the loop filter bandwidth can be reduced further to reduce the phase noise at the adjacent channel. the filter rolls off at 20 db per decade. spurious levels in the case where the output power is quite high, a reduced loop filter bandwidth reduces the spurious levels even further, and provides additional margin on the specification. the following sections provide examples of loop filter designs for typical applications in specific frequencies. pa matching the adf7012 exhibits optimum performance in terms of transmit power and current consumption only if the rf output port is properly matched to the antenna impedance. zopt_pa depends primarily on the required output power, and the frequency range. selecting the optimum zopt_pa helps to minimize the current consumption. this data sheet contains a number of matching networks for common fre- quency bands. under certain conditions it is recommended to obtain a suitable zopt_pa value by means of a load-pull measurement. antenna lpf rf out zopt_pa pa dv dd 04617-0-033 figure 38. adf7012 with harmonic filter the impedance matching values provided in the next section are for 50 environments. an additional matching network may be required after the harmonic filter to match to the antenna impedance. this can be incorporated into the filter design itself in order to reduce external components. transmit protocol and coding considerations 04617-0-034 preamble sync word id field data field crc figure 39. typical format of a transmit protocol a dc-free preamble pattern such as 10101010 is recom- mended for fsk/ask/ook demodulation. preamble patterns with longer run-length constraints such as 11001100. can also be used. however, this can result in a longer synchronization time of the received bit stream in the chosen receiver.
adf7012 rev. a | page 19 of 28 application examples 04617-0-035 figure 40. applications diagram with harmonic filter
adf7012 rev. a | page 20 of 28 315 mhz operation the recommendations presented here are guidelines only. the design should be subject to internal testing prior to fcc site testing. matching components need to be adjusted for board layout. the fcc standard 15.231 regulates operation in the band from 260 mhz to 470 mhz in the us. this is used generally in the transmission of rf control signals, such as in a satellite- decoder remote control, or remote keyless entry system. the band cannot be used to send any continuous signal. the maximum output power allowed is governed by the duty cycle of the system. a typical design example for a remote control is provided. design criteria 315 mhz center frequency fsk/ook modulation 1 mw output power house range meets fcc 15.231 the main requirements in the design of this remote are a long battery life and sufficient range. it is possible to adjust the output power of the adf7012 to increase the range depending on the antenna performance. the center frequency is 315 mhz. because the adf7012 vco is not recommended for operation in fundamental mode for frequencies below 400 mhz, the vco needs to operate at 630 mhz. figure 36 implies an inductor value of, or close to, 7.6 nh. the chip inductor chosen = 7.5 nh (0402cs-7n5 from coilcraft). coil inductors are recommended to provide sufficient q for oscillation. crystal and pfd phase noise requirements are not excessive as the adjacent channel power requirement is ?20 db. the pfd is chosen to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. pfd = 3.6864 mhz ? power-up time 1.6 ms. figure 10 shows a typical power-on time for a 4 mhz crystal. n-divider the n-divider is determined as being n int = 85 n frac = (1850)/4096 vco divide-by-2 is enabled deviation the deviation is set to 50 khz to accommodate simple receiver architecture. the modulation steps available are in 3.6864 mhz/2 14 : modulation steps = 225 hz modulation number = 50 khz/225 hz = 222 bias current because low current is desired, a 2.0 ma vco bias can be used. additional bias current reduces any spur, but increases current consumption. the pa bias can be set to 5.5 ma and can achieve 0 dbm. loop filter bandwidth the loop filter is designed with the adisimsrd design studio. the loop bandwidth design is straightforward because the 20 db bandwidth is generally of the order of >400 khz (0.25% of center frequency). a loop bandwidth of close to 100 khz strikes a good balance between lock time and spurious suppression. if it is found that pulling of the vco is more than desired in ook mode, the bandwidth could be increased. design of harmonic filter the main requirement of the harmonic filter should ensure that the third harmonic level is < ?41.5 dbm. a fifth-order chebyshev filter is recommended to achieve this, and a suggested starting point is given next. the pi format is chosen to minimize the more expensive inductors. component valuescrystal: 3.6864 mhz loop filter i cp 0.866 ma lbw 100 khz c1 680 pf c2 12 nf c3 220 pf r1 1.1 k r2 3 k matching l1 56 nh l2 1 nf c14 470 pf harmonic filter l4 22 nh l5 22 nh c15 3.3 pf c16 8.2 pf c17 3.3 pf
adf7012 rev. a | page 21 of 28 433 mhz operation the recommendations here are guidelines only. the design should be subject to internal testing prior to etsi site testing. matching components need to be adjusted for board layout. the etsi standard en 300-220 governs operation in the 433.050 mhz to 434.790 mhz band. for many systems, 10% duty is sufficient for the transmitter to output 10 dbm. design criteria 433.92 mhz center frequency fsk modulation 10 mw output power 200 m range meets etsi 300-220 the main requirement in the design of this remote is a long battery life and sufficient range. it is possible to adjust the output power of the adf7012 to increase the range depending on the antenna performance. the center frequency is 433.92 mhz. it is possible to operate the vco at this frequency. figure 36 shows the inductor value vs. center frequency. the inductor chosen is 22 nh. coilcraft inductors such as 0603-cs-22nxjbu are recommended. crystal and pfd the phase noise requirement is such to ensure the power at the edge of the band is < ?36 dbm. the pfd is chosen to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. pfd = 4.9152 mhz ? power-up time 1.6 ms. figure 10 shows a typical power-up time for a 4 mhz crystal. n-divider the n divider is determined as being: nint = 88 nfrac = (1152)/4096 vco divide-by-2 is not enabled deviation the deviation is set to 50 khz to accommodate a simple receiver architecture. the modulation steps available are in 4.9152 mhz/2 14 : modulation steps = 300 hz modulation number = 50 khz/300hz = 167 bias current because low current is desired, a 2.0 ma vco bias can be used. additional bias current reduces any spurious, but increases current consumption. the pa bias can be set to 5.5 ma and achieve 10 dbm. loop filter bandwidth the loop filter is designed with adisimsrd design studio. the loop bandwidth design requires that the channel power be < ?36 dbm at 870 khz from the center. a loop bandwidth of close to 160 khz strikes a good balance between lock time for data rates, including 32 kbps and spurious suppression. if it is found that pulling of the vco is more than desired in ook mode, the bandwidth could be increased. design of harmonic filter the main requirement of the harmonic filter should ensure that the third harmonic level is < ?30 dbm. a fifth-order chebyshev filter is recommended to achieve this, and a suggested starting point is given next. the pi format is chosen to minimize the more expensive inductors. component valuescrystal: 4.9152 mhz loop filter icp 2.0 ma lbw 100 khz c1 680 pf c2 12 nf c3 270 pf r1 910 r2 3.3 k matching l1 22 nh l2 10 pf c14 470 pf harmonic filter l4 22 nh l5 22 nh c15 3.3 pf c16 8.2 pf c17 3.3 pf
adf7012 rev. a | page 22 of 28 868 mhz operation the recommendations here are guidelines only. the design should be subject to internal testing prior to etsi site testing. matching components need to be adjusted for board layout. the etsi standard en 300-220 governs operation in the 868 mhz to 870mhz band. the band is broken down into several subbands each having a different duty cycle and output power requirement. narrowband operation is possible in the 50khz channels, but both the output power and data rate are limited by the ?36 dbm adjacent channel power specification. there are many different applications in this band, including remote controls for security, sensor interrogation, metering and home control. design criteria 868.95 mhz center frequency (band 868.7mhz ? 869.2 mhz) fsk modulation 12 dbm output power 300 m range meets etsi 300-220 38.4 kbps data rate the design challenge is to enable the part to operate in this particular subband and meet the acp requirement 250 khz away from the center. the center frequency is 868.95 mhz. it is possible to operate the vco at this frequency. figure 31 shows the inductor value vs. center frequency. the inductor chosen is 1.9 nh. coilcraft inductors such as 0402-cs-1n9xjbu are recommended. crystal and pfd the phase noise requirement is such to ensure the power at the edge of the band is < ?36 dbm. this requires close to ?100 dbc/hz phase noise at the edge of the band. the pfd is chosen to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. a pfd of < 6 mhz places the largest pfd spur at a frequency of greater than 862 mhz, and so reduces the requirement on the spur level to ?36 dbm instead of ?54 dbm. pfd = 4.9152 mhz ? power up-time 1.6 ms. figure 10 shows a typical power-on time for a 4mhz crystal. n-divider the n divider is determined as being: nint = 176 nfrac = (3229)/4096 vco divide-by-2 is not enabled. deviation the deviation is set to 19.2 khz to accommodate a simple receiver architecture and ensure that the modulation spectrum is narrow enough to meet the adjacent channel power (acp) requirements. the modulation steps available are in 4.9152 mhz/2 14 : modulation steps = 300 hz modulation number = 19.2 khz/300 hz = 64. bias current because low current is desired, a 2.5 ma vco bias can be used. additional bias current reduces any spurious, but increases current consumption. a 2.5 ma bias current gives the best spurious vs. phase noise trade-off. the pa bias should be set to 7.5 ma to achieve 12 dbm. loop filter bandwidth the loop filter is designed with adisimsrd design studio. the loop bandwidth design requires that the channel power be < ?36 dbm at 250 khz from the center. a loop bandwidth of close to <60 khz is required to bring the phase noise at the edge of the band sufficiently low to meet the acp specification. this represents a compromise between the data rate requirement and the phase noise requirement. design of harmonic filter the main requirement of the harmonic filter should ensure that the second and third harmonic levels are < ?30 dbm. a fifth- order chebyshev filter is recommended to achieve this, and a suggested starting point is given next. the pi format is chosen to minimize the more expensive inductors. component valuescrystal: 4.9152 mhz loop filter icp 1.44 ma lbw 60 khz c1 1.5 nf c2 22 nf c3 560 pf r1 390 r2 910 matching l1 27 nh l2 6.2 nh c14 470 pf harmonic filter l4 8.2 nh l5 8.2 nh c15 4.7 pf c16 6.8 pf c17 4.7 pf
adf7012 rev. a | page 23 of 28 915 mhz operation the recommendations here are guidelines only. the design should be subject to internal testing prior to fcc site testing. matching components need to be adjusted for board layout. fcc 15.247 and fcc 15.249 are the main regulations governing operation in the 902 mhz to 928 mhz band. fcc 15.247 requires some form of spectral spreading. typically, the adf7012 would be used in conjunction with the frequency hopping spread spectrum (fhss) or it may be used in conjunction with the digital modulation standard which requires large deviation frequencies. output power of < 1 w is tolerated on certain spreading conditions. compliance with fcc 15.249 limits the output power to ?1.5 dbm, but does not require spreading. there are many different applications in this band, including remote controls for security, sensor interrogation, metering, and home control. design criteria 915.2mhz center frequency fsk modulation 10 dbm output power 200 m range meets fcc 15.247 38.4 kbps data rate the center frequency is 915.2 mhz. it is possible to operate the vco at this frequency. figure 36 shows the inductor value vs. center frequency. the inductor chosen is 1.6 nh. coilcraft inductors such as 0603-cs-1n6xjbu are recommended. additional hopping frequencies can easily be generated by changing the n value. crystal and pfd the phase noise requirement is such to ensure that the 20 db bandwidth requirements are met. these are dependent on the channel spacing chosen. a typi cal channel spacing would be 400 khz, which would allow 50 channels in 20 mhz and enable the design to avoid the edges of the band. the pfd is chosen to minimize spurious levels. there are beat note spurious levels at 910 mhz and 920 mhz, but the level is usually significantly less than the modulation power. they are also attenuated quickly by the loop filter to ensure a quick crystal power-up time. pfd = 10 mhz ? power-up time 1.8 ms (approximately). figure 10 shows a typical power-on time for a 4 mhz crystal. n-divider the n divider is determined as being: nint = 91 nfrac = (2130)/4096 vco divide-by-2 is not enabled deviation the deviation is set to 19.2 khz to accommodate a simple receiver architecture, and to ensure the available spectrum is used efficiently. the modulation steps available are in 10 mhz/2 14 : modulation steps = 610 hz modulation number = 19.2 khz/610 hz = 31. bias current because low current is desired, a 3 ma vco bias can be used and still ensure oscillation at 928 mhz. additional bias current reduces any spurious noise, but increases current consumption. a 3 ma bias current gives the best spurious vs. phase noise trade-off. the pa bias should be set to 5.5 ma to achieve 10 dbm power. loop filter bandwidth the loop filter is designed with the adisimsrd design studio. a data rate of 170 khz is chosen, which allows for data rates of > 38.4 kbps. it also attenuates the beat note spurs quickly to ensure they have no effect on system performance. design of harmonic filter the main requirement of the harmonic filter should ensure that the third harmonic level is < ?41.5 dbm. a fifth-order chebyshev filter is recommended to achieve this, and a sug- gested starting point is given next. the pi format is chosen to minimize the number of inductors in the system. component valuescrystal: 10 mhz loop filter icp 1.44 ma lbw 170 khz c1 470 pf c2 12 nf c3 120 pf r1 470 r2 1.8 k matching l1 27 nh l2 6.2 nh c14 470 pf harmonic filter l4 8.2 nh l5 8.2 nh c15 4.7 pf c16 6.8 pf c17 4.7 pf
adf7012 rev. a | page 24 of 28 register descriptions register 0: r register d1 crystal doubler 0 crystal doubler off 1 crystal doubler on x1 xoeb 0 xtal oscillator on (default) 1 xtal oscillator off od2 od1 output divider 0 disabled 0 divide by 2 1 divide by 4 1 0 1 0 1 divide by 8 va2 va1 vco adjust 0 no vco adjustment 0 ....... 1 ....... 1 0 1 0 1 max vco adjustment cl4 cl3 cl2 cl1 clk out divide ratio 0 2 0 0 0 . . 1 1 0 1 0 . . 0 4 6 8 . . 0 1 1 0 . . 0 0 0 1 . . . 16 (default) .. . 1 28 11 1 11 30 rl4rl3rl2rl1 rf r counter divide ratio 0 1 0 0 0 . . . 1 0 1 0 . . . 2 3 4 . . 0 1 1 0 . . 0 0 0 1 . . . . 10 . 01 12 11 01 13 10 11 14 11 11 15 address bits 11-bit frequency error correction 4-bit r divider clock out divider vco adjust output divider xoeb crystal doubler va1 od2 od1 va2 cl4 f7 f8 f9 f10 r3 r4 d1 cl1 cl2 cl3 x1 f11 r1 r2 f6 f5 c2 (0) c1 (0) f1 f2 f3 f4 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 04617-0-027 f-counter offset +1023 +1022 . +1 +0 ?1 ?2 ?3 ?1023 ?1024 f11 0 0 0 0 0 1 1 . 1 1 ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... f3 1 1 . 0 0 1 1 . 0 0 f2 0 0 . 0 0 1 1 . 0 0 f1 0 1 . 1 0 1 0 . 1 0 figure 41. register 0: r register
adf7012 rev. a | page 25 of 28 register 1: n-counter latch p1 prescaler 04/5 18/9 the n-value chosen is a minimum of p 2 + 3p + 3. for prescaler 8/9 this means a minimum n-divide of 91. for prescaler 4/5 this means a minimum n-divide of 31. n4 n3 n2 n1 n-counter divide ratio 0 0 0 0 . . . 1 0 1 0 . . . 0 1 2 . . . 0 0 1 . . . 0 0 0 . . . 1 254 11 1 11 n7 n6 n5 0 0 0 . . . 1 0 0 0 . . . 0 0 0 . . . 1 1 1 11 n8 0 0 0 . . . 1 1 255 address bits 12-bit fractional-n 8-bit integer-n prescaler p1 m7 m8 m9 m10 n2 n3 n5 n6 n7 n8 n4 m11 m12 n1 m6 m5 c2 (0) c1 (1) m1 m2 m3 m4 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db1 db0 db2 db3 04617-0-028 modulus divide ratio 0 1 2 . . . 4092 4093 4094 4095 m10 0 0 0 . . . 1 1 1 1 ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... m3 0 0 0 . . . 1 1 1 1 m2 0 0 1 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 m12 0 0 0 . . . 1 1 1 1 m11 0 0 0 . . . 1 1 1 1 figure 42. register 1: n-counter latch
adf7012 rev. a | page 26 of 28 register 2: modulation register g1 gaussian ook must be low 0 off 1 on power amplifier output level .d2d1 .p a o f f . . 1 0 1 . 1 0 0 . pa max 1 d6 . . . . 0 . . 11 if amplitude shift keying selected, txdata = 0 .p2p1 .p a o f f . . 1 0 1 . 1 0 0 . pa max 1 p6 . . . . 0 . . 11 d3 d2 d1 f deviation 0 pll mode 0 0 0 . 1 0 1 0 1 . 1 1f step 2f step 3f step ....... 511 f step 0 0 1 1 . 1 d9 ....... ....... ....... ....... ....... ....... ....... 0 0 0 0 . 1 if frequency shift keying selected f step = f pfd /2 14 if gaussian frequency shift keying selected address bits mod control index counter gook power amplifier modulation deviation test bits gfsk mod control mc3 p4 p5 p6 d1 d5 d6 d8 d9 mc1 mc2 ic1 ic2 d7 d2 d3 d4 p3 p2 c2 (1) c1 (0) s1 s2 g1 p1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 0 4617-0-029 s2 s1 modulation scheme 0f s k 0g f s k 1a s k 1 0 1 0 1 ook d7 d3 d2 d1 divider factor 0 0 0 0 00 1 0 13 1 2 0 0 1 1 0 0 0 0 . 1... ....... ....... ....... ....... ....... ....... ....... . 1 ....... 127 . 1 . 1 mc3 mc2 mc1 gfsk mod control 0 0 00 11 0 0 . 1 . 1 . 7 . 1 ic2 ic1 index counter 0 0 1 1 016 1 0 1 128 32 64 figure 43. register 2: modulation register
adf7012 rev. a | page 27 of 28 register 3: function register i1 data invert 0normal 1inverted pd3 clk out 0clk out off 1clk out on pd2 pa enable 0paoff 1paon cp4 bleed down 0bleed off (default) 1bleedon vd1 vco disable 0vcoon 1vcooff ld1 ld precision 0 3 cycles (default) 15 cycles cp3 bleed up 0 bleed off (default) 1 bleed on pd1 pll enable 0plloff 1pllon cp2 cp1 charge pump current 00 . 3 m a 00 . 9 m a 11 . 5 m a 1 0 1 0 12.1ma m4 m3 m2 m1 muxout 0 logic low 0 0 0 0 0 0 0 1 0 1 0 1 0 logic high invalid mode ? do not use regulator ready (default) digital lock detect analog lock detect 0 0 1 1 0 0 0 0 0 0 1 1 1 r divider/2 output 01 1 11 n divider/2 output 10 00 rf r divider output 11 00 data rate 10 10 battery measure is < 2.35v 11 10 battery measure is < 2.75v 10 01 battery measure is < 3v 11 01 battery measure is < 3.25v 10 11 normal test modes 11 11 - test modes vb4 vb3 vb2 vb1 vco bias current 0 0.5ma 0 . 1 1 0 . 1 1ma . 8ma 0 1 . 1 0 0 . 1 pa3 pa2 pa1 pa bias 5 a 0 1 0 . 6 a 7 a . 0 0 1 . 0 0 0 . . 1 . 12 a . 1 . 1 address bits charge pump bleed current muxout pa bias vco bias pll test modes sd test modes ld precision pll enable pa enable clkout enable data invert vco disable pt1 pt4 pt5 st1 st2 st3 st4 pt3 pt2 pa3 cp3 cp4 vd1 m1 ld1 vb1 vb3 vb4 pa1 pa2 vb2 m2 m3 m4 cp2 cp1 c2 (1) c1 (1) pd1 pd2 pd3 i1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 04617-0-030 figure 44. register 3: function register
adf7012 rev. a | page 28 of 28 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 45. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range package descri ption package option frequency range adf7012bru 1 ? 40c to +85c 24-lead tssop ru-24 75 mhz to 1 ghz adf7012bru-reel 1 ? 40c to +85c 24-lead tssop, 13 reel ru-24 75 mhz to 1 ghz adf7012bru-reel7 1 ? 40c to +85c 24-lead tssop, 7 reel ru-24 75 mhz to 1 ghz adf7012bruz 1 ? 40c to +85c 24-lead tssop ru-24 75 mhz to 1 ghz ADF7012BRUZ-RL 1 ? 40c to +85c 24-lead tssop, 13 reel ru-24 75 mhz to 1 ghz ADF7012BRUZ-RL7 1 ? 40c to +85c 24-lead tssop, 7 reel ru-24 75 mhz to 1 ghz eval-adf7012dbz1 1 evaluation board 902 mhz to 928 mhz eval-adf7012dbz2 1 evaluation board 860 mhz to 880 mhz eval-adf7012dbz3 1 evaluation board 418 mhz to 435 mhz eval-adf7012dbz4 1 evaluation board 310 mhz to 330 mhz eval-adf7012dbz5 1 evaluation board 75 mhz to 1 ghz 1 z = rohs compliant part. ?2007C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04617-0-6 /09(a)

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